1. Field of the Invention
The present invention described herein relates to a multichip, and more particularly, to a multichip capable of testing a memory and a method of testing the multichip.
2. Description of the Related Art
System-in-Package (SiP), Multichip Package (MCP), and Package-on-Package (POP) technologies are widely used to achieve low power consumption and miniaturization of electronic application products such as the latest portable smart phones, personal digital assistants (PDAs), navigation devices, etc.
FIG. 1 is a block diagram of a SiP 10 in embodiments of a multichip. Referring to FIG. 1, the SiP 10 combines a plurality of Large Scale Integrated circuits (LSIs) into a single package to form a system. FIG. 2 is a block diagram of a MCP 20 in embodiments of a multichip. Referring to FIG. 2, the MCP 20 stacks various kinds of memory chips in one package. The MCP 20 combines necessary memories according to application to realize various functions. FIG. 3 is a block diagram of a POP 30 in embodiments of a multichip. Referring to FIG. 3, the POP 30 stacks two Ball Grid Array (BGA) packages sequentially. A lower BGA package includes a metal ball or a bump arranged therebelow, and includes a footprint (land) at the top surface to receive a corresponding upper BGA package.
According to the above technologies, more than two chips such as a single control chip and a single memory chip are stacked according to a stack process. The stack process is performed using a plurality of acceptable single chips, which are selected according to a test. However, even though each of the selected single chips is acceptable, defects relating to timing, load, and resistance may occur at an interface between the chips as a result of the stacking process.
However, a package level test is not performed on a typical multichip after the stack process. Additionally, a test pattern is also limited while testing a single chip.